A frequency divider is used to reduce the frequency of an input signal.
FIG. 9 is a circuit diagram illustrating a prior art frequency divider.
The frequency divider of FIG. 9 comprises transmission gates T4 and T5 that are turned on or off when a positive phase clock signal and a negative phase clock signal are input to the gate terminals, respectively, an element S3 having function of amplification (hereinafter referred to as an amplification element), and an element S4 having functions of inversion and amplification (hereinafter referred to as an inversion and amplification element).
The amplification element S3 is interposed between an output terminal of the transmission gate T4 and an input terminal of the transmission gate T5. The inversion and amplification element S4 is interposed between an output terminal of the transmission gate T5 and an input terminal of the transmission gate T4.
In this prior art frequency divider, an input terminal of a positive phase clock CLK is connected to the gate terminal of the transmission gate T4, and an input terminal of a negative phase clock CLK is connected to the gate terminal of the transmission gate T5. The amplification element S3 is interposed between the output terminal of the transmission gate T4 and the input terminal of the transmission gate T5. The inversion and amplification element S4 is interposed between the output terminal of the transmission gate T5 and the input terminal of the transmission gate T4. An output terminal OUT of the circuit from which a signal obtained by frequency-dividing the positive or negative phase clock signal is output is connected to the output terminal of the element S4. That is, this frequency divider comprises two transmission gates T4 and T5, two input terminals of clock signals having opposite phases, an element S3 having a function of amplification, and an element S4 having functions of inversion and amplification.
FIG. 10 illustrates an example of the frequency divider shown in FIG. 9 in which a noninverting logic circuit is employed as the amplification element S3 and an inverting logic circuit is employed as the inversion and amplification element S4. In FIG. 10, a noninverting logic circuit G5 corresponds to the amplification element S3 of FIG. 9, and an inverting logic circuit G6 corresponds to the inversion and amplification element S4 of FIG. 9. A node N11 corresponds to the input terminal of the transmission gate T4, a node N12 corresponds to the output terminal of the transmission gate T4, a node N13 corresponds to the input terminal of the transmission gate T5, and a node N14 corresponds to the output terminal of the transmission gate T5.
FIG. 15 illustrates a direct coupled FET logic (DCFL) circuit as an example of the inverting logic circuit G6 shown in FIG. 10. In FIG. 15, reference numeral 151 designates an enhancement type FET having a gate connected to an input terminal IN, and numeral 152 designates a diode coupled depletion type FET. These FETs 151 and 152 are connected in series between a power supply V.sub.DD and ground GND. The depletion type FET 152 serves as a load for supplying current to the enhancement type FET 151. When a signal is input to the input terminal IN, the input signal is logically inverted and output from the junction of the FETs 151 and 152. These FETs 151 and 152 make an inverting logic circuit corresponding to G6 of FIG. 10. Reference numerals 153 and 154 designate an enhancement type FET and a depletion type FET identical to the enhancement type FET 151 and the depletion type FET 152, respectively. These FETs 153 and 154 make an inverting logic circuit 156 identical to the inverting logic circuit 155. These two inverting logic circuits 155 and 156 make a noninverting logic circuit corresponding to G5 of FIG. 10.
FIG. 11 illustrates a timing chart of the frequency divider shown in FIG. 10. Hereinafter, the operation of the frequency divider will be described using FIG. 11.
The positive phase clock CLK and the negative phase clock CLK alternate "High" level and "Low" level (hereinafter referred to as "H" level and "L" level or simply as "H" and "L", respectively) at constant frequency. When the positive phase clock CLK is at "L" level and the node N11 is at "H" level, since the transmission gate T4 is in the OFF state, the signal "H" at the node N11 is not transferred to the node N12.
When the positive phase clock CLK is inverted to "H" level, the transmission gate T4 is turned on, and transfer of the signal "H" at the node N11 toward the node N12 starts. That is, inversion of the node N12 to "H" level is delayed by the delay time of the transmission gate T4 after the inversion of the positive phase clock CLK. The signal "H" at the node N12 is amplified by the noninverting logic circuit G5, and the node N13 is inverted to "H" level after a time interval equivalent to the delay time of the noninverting logic circuit G5. At this time, since the negative phase clock CLK is at "L" level, the signal "H" at the node N13 is not transferred to the node N14. When the negative phase clock CLK is inverted to "H" level, the transmission gate T5 is turned on, and transfer of the signal "H" at the node N13 toward the node N14 starts.
Inversion of the node N14 to "H" level is delayed by the delay time of the transmission gate T5 after the inversion of the negative phase clock CLK to "H" level. Thereafter, the signal "H" at the node N14 is inverted and amplified by the inversion and amplification circuit G6, and the node N11 is inverted to "L" level after a time interval equivalent to the delay time of the inverting logic circuit G6. At this time, since the clock CLK is at "L" level, the signal "L" at the node N11 is not transferred to the node N12. When the positive phase clock CLK is inverted to "H" level, transfer of the signal "L" at the node N11 toward the node N12 starts. In this way, the signal at the node N12 is inverted during one period of the clock.
As described above, the node N11 changes from "H" level to "L" level during one period of the clock CLK, whereby a signal having a frequency equivalent to 1/2 of the frequency of the clock CLK is produced.
In order to stably operate the prior art frequency divider, the following conditions must be satisfied.
The "H" signal at the node N11 is transferred after the inversion of the clock CLK to "H" level. This "H" signal is inverted to a "L" signal while traveling through the transmission gate T4, the noninverting logic circuit G5, the transmission gate T5, and the inverting logic circuit G6, and the "L" signal returns to the node N11.
At this time, as shown in FIG. 11, if the clock CLK is at "L" level when the node N11 is inverted to "L" level, the frequency of the clock is accurately reduced to 1/2. However, if the node N11 is not inverted to "L" level by the time the clock CLK is inverted to "H" level because of an increase in the frequency of the clock or increase in the delay time, the clock is not accurately synchronized with the transmission gate T4. As the result, the frequency of the clock is not accurately reduced by 1/2.
In other words, the total of the delay times of the transmission gate T4, the noninverting logic circuit G5, the transmission gate T5, and the inverting logic circuit G6 must be shorter than one period of the clock CLK.
As the result, in the above-described prior art frequency divider, since the delay time required for inverting the generated frequency-divided signal is too long to achieve accurate frequency division with a high-speed clock. Furthermore, both the positive phase clock signal and the negative phase clock signal are required.
FIG. 12 is a circuit diagram illustrating another frequency divider according to the prior art. This frequency divider includes an amplification element performing differential amplification, whereby highly-reliable operation is achieved compared to the prior art circuit shown in FIG. 9.
The prior art frequency divider shown in FIG. 12 comprises two transmission gates T6 and T7 that are turned on or off when the positive phase clock CLK is input to the gate terminals, two transmission gates T8 and T9 that are turned on or off when the negative phase clock CLK is input to the gate terminals, and two amplification elements S5 and S6 each having complementary input and output terminals (hereinafter referred to as complementary input and output amplification elements). The element S5 is interposed between the output terminals of the transmission gates T6 and T7 and the input terminals of the transmission gates T8 and T9. The element S6 is interposed between the output terminals of the transmission gates T6 and T7 and the input terminals of the transmission gates T6 and T7. The complementary output terminals of the element S6 are cross-connected to the input terminals of the transmission gates T6 and T7.
In this frequency divider, the input terminal of the positive phase clock CLK is connected to the gate terminals of the transmission gates T6 and T7. The input terminal of the negative phase clock CLK is connected to the gate terminals of the transmission gates T8 and T9. The complementary input and output amplification element S5 is interposed between the output terminals of the transmission gates T6 and T7 and the input terminals of the transmission gates T8 and T9. The complementary input and output amplification element S6 is interposed between the output terminals of the transmission gates and the input terminals of the transmission gates T6 and T7. The complementary output terminals of the element S6 are cross-connected to the input terminals of the transmission gates T6 and T7. Two output terminals OUT and OUT from which positive and negative phase signals obtained by frequency-dividing the positive and negative phase clock signals CLK And CLK are respectively output are connected to the complementary output terminals of the element S6. That is, this frequency divider comprises four transmission gates T6, T7, T8, and T9, two input terminals from which opposite phase clock signals CLK and CLK are applied to the transmission gates T6 and T7 and the transmission gates T8 and T9, respectively, and two complementary input and output amplification elements S5 and S6.
FIG. 13 is a circuit diagram illustrating an example of the frequency divider of FIG. 12 in which complementary input and output noninverting logic circuits are employed as the complementary input and output amplification elements S5 and S6.
In FIG. 13, a complementary input and output noninverting logic circuit G7 corresponds to the complementary input and output amplification element S5 of FIG. 12, and a complementary input and output noninverting logic circuit G8 corresponds to the inversion and amplification element S6 of FIG. 12.
A noninverting input terminal and a noninverting output terminal of the noninverting logic circuit G7 are connected to an output terminal of the transmission gate T6 and an input terminal of the transmission gate T8, respectively. An inverting input terminal and an inverting output terminal of the circuit G7 are connected to an output terminal of the transmission gate T7 and an input terminal of the transmission gate T9, respectively.
A noninverting input terminal and a noninverting output terminal of the noninverting logic circuit G8 are connected to an output terminal of the transmission gate T8 and an input terminal of the transmission gate T7, and an inverting input terminal and an inverting output terminal of the circuit G8 are connected to an output terminal of the transmission gate T9 and an input terminal of the transmission gate T6, respectively.
In FIG. 13, nodes N31 and N35 correspond to the input terminals of the transmission gates T6 and T7, respectively. Nodes N32 and N36 correspond to the output terminals of the transmission gates T6 and T7, respectively. Nodes N33 and N37 correspond to the input terminals of the transmission gates T8 and T9, respectively. Nodes N34 and N38 correspond to the output terminals of the transmission gates T8 and T9, respectively.
FIG. 16 illustrates a source coupled FET logic (SCFL) circuit as an example of the noninverting amplification circuit of FIG. 12.
In FIG. 16, reference numerals 161 and 162 designate enhancement type FETs having gates to which a positive phase input terminal IN and a negative phase input terminal IN are connected, respectively. Reference numeral 163 designates a current source interposed between a common source of these FETs and a power supply V.sub.SS. A diode coupled depletion type FET 172 is employed as the current source 163. Alternatively, a resistor 173 may be interposed between the source of the FET 172 and the power supply V.sub.SS. Reference numerals 164 and 165 designate resistors interposed between ground GND and drains of the FETs 161 and 162, respectively. Reference numerals 166 and 167 designate enhancement type FETs having drains connected to the ground GND and gates connected to the drains of the FETs 161 and 162, respectively. Reference numerals 168 and 169 designate diodes having anodes connected to the sources of the FETs 166 and 167, respectively. Reference numerals 170 and 171 designate current sources interposed between the power supply V.sub.SS and cathodes of the diodes 168 and 169, respectively. The junction of the cathode of the diode 168 and the current source 170 is connected to the negative phase output terminal OUT, and the junction of the cathode of the diode 169 and the current source 171 is connected to a positive phase output terminal OUT.
In the circuit shown in FIG. 16, signals having opposite phases respectively input to the input terminals IN and IN are subjected to differential amplification in the FETs 161 and 162, respectively, and signals having phases opposite to the signals at the input terminals IN and IN appear at the drains of the FETs 161 and 162, respectively. These signals are transferred through the source follower FETs 166 and 167 and appear at the output terminals OUT and OUT, respectively, so that amplified signals having the same phases as the signals at the input terminals IN and IN are output from the output terminals OUT and OUT, respectively.
FIG. 14 is a timing chart of the frequency divider shown in FIG. 13. Hereinafter, the operation of the frequency divider will be described using FIG. 14.
Also in this frequency divider, the same conditions as described with respect to the frequency divider according to the first prior art must be satisfied to achieve a desired frequency dividing operation.
More specifically, the positive phase clock CLK and the negative phase clock CLK alternate "H" level and "L" level at constant frequency. When the positive phase clock CLK is at "L" level and the nodes N31 and N35 are at "H" level and "L" level, respectively, both of the transmission gates T6 and T7 are in OFF state, so that signals "H" and "L" at the nodes N31 and N35 are not transferred to the nodes N32 and N36.
When the positive phase clock CLK is inverted to "H" level, the transmission gates T6 and T7 are turned on, and transfer of the signals "H" and "L" at the nodes N31 and N35 toward the nodes N32 and N36 starts. That is, after the inversion of the positive phase clock CLK to "H" level, inversion of the node N32 (N36) to "H" level ("L" level) is delayed by the delay time of the transmission gate T6 (T7). The signals "H" and "L" at the nodes N32 and N36 are subjected to differential amplification in the noninverting logic circuit G7, and the nodes N33 and N37 are inverted to "H" and "L" levels, respectively, after a time interval equivalent to the delay time of the noninverting logic circuit G7. At this time, since the negative phase clock CLK is at "L" level, the signals "H" and "L" at the nodes N33 and N37 are not transferred to the nodes N34 and N38, respectively.
When the negative phase clock CLK is inverted to "H" level, the transmission gates T8 and T9 are turned on, and transfer of the signals "H" and "L" at the nodes N33 and N37 toward the nodes N34 and N38, respectively, starts.
More specifically, after the inversion of the negative clock CLK to "H" level, the nodes N34 and N38 are inverted to "H" and "L" levels after a time interval equivalent to the delay time of the transmission gates T8 and T9, respectively. The signals "H" and "L" at the nodes N34 and N38 are amplified without being inverted by the noninverting logic circuit G8. Since the outputs of the noninverting logic circuit G8 are cross-connected to the nodes N31 and N35, the nodes N31 and N35 are inverted to "L" and "H" levels, respectively, after a time interval equivalent to the delay time of the noninverting logic circuit G8. At this time, since the clock CLK is at "L" level, the signals "L" and "H" at the nodes N31 and N35 are not transferred to the nodes N32 and N36, respectively.
When the positive phase clock CLK is inverted to "H" level, transfer of the signals "L" and "H" at the nodes N31 and N35 toward the nodes N32 and N36, respectively, starts. In this way, the signals at the nodes N32 and N36 are inverted during one period of the clock.
As described above, the nodes N31 and N35 change from "H" level to "L" level during one period of the clock CLK, and a signal having a frequency equivalent to 1/2 of the frequency of the clock CLK is produced.
In order to accurately operate this prior art frequency divider, the following conditions must be satisfied.
Transfer of the signal "H" at the node N31 starts after the inversion of the clock CLK to "H" level. This signal "H" travels through the transmission gate T6, the noninverting logic circuit G7, the transmission gate T8, and the noninverting logic circuit G8 and returns to the node N35. On the other hand, transfer of the signal "L" at the node N35 starts after the inversion of the clock CLK to "H" level. This signal "L" travels through the transmission gate T7, the noninverting logic circuit G7, the transmission gate T9, and the noninverting logic circuit G8 and returns to the node N31.
As shown in FIG. 14, if the clock CLK is at "L" level when the node N31 is inverted to "L" level, the frequency of the clock is accurately reduced to 1/2. However, if the node N31 has not been inverted to "L" level by the time the clock CLK is inverted to "H" level because of an increase in the frequency of an the clock or increase in the delay time, the clock is not accurately synchronized in the transmission gate T4 and the frequency of the clock is not accurately reduced by 1/2.
In other words, each of the total of the delay times of the transmission gate T6, the complementary input and output noninverting logic circuit G7, the transmission gate T8, and the complementary input and output noninverting logic circuit G8 and the total of the delay times of the transmission gate T7, the complementary input and output noninverting logic circuit G7, the transmission gate T9, and the complementary input and output noninverting logic circuit G8 must be shorter than the period of the clock CLK.
As described above, also in this second frequency divider according to the prior art, the delay time required for inverting the frequency-divided signal is too long to achieve accurate frequency division with a high-speed clock. In addition, both the positive phase clock and the negative phase clock are needed.